A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having a non-volatile memory of a stacked gate electrode structure formed on a gate insulating film (a tunneling insulating film) on the surface of a semiconductor substrate and to its manufacture method. The stacked gate electrode structure is constituted of a floating gate electrode (typically a polysilicon layer), an inter-electrode insulating film (typically an ONO stacked insulating film of an oxide film/a nitride film/an oxide film) and a control gate (typically a polysilicon layer).
B) Description of the Related Art
Many non-volatile semiconductor memories such as flash memories are used which utilize two-layer polysilicon layers. A flash memory is formed by forming a tunneling oxide film on a silicon substrate, forming a floating gate of a first polysilicon layer on the tunneling oxide film, and forming a control gate of a second polysilicon layer with an inter-electrode insulating film being interposed therebetween. An ONO film of a lamination of an oxide film/a nitride film/an oxide film is used as the inter-electrode insulating film. By applying a voltage between the control gate and substrate, it is possible to inject (write) charges from the substrate to the floating gate and to drain (erase) charges in the floating gate to the substrate.
The floating gate is formed independently in each memory cell. A control gate is used in common by a plurality of memory cells. For electric insulation between the control gate and floating gate, the ONO film covers the upper surface and side wall of the floating gate covered with the control gate.
In an integrated peripheral circuit area, the first polysilicon layer is removed and a single-layer gate electrode is formed by the second polysilicon layer. In a flash memory, unique processes such as side wall oxidation are executed after the laminated gate electrodes are formed. If these unique processes are executed after the gate electrodes of transistors in the peripheral circuit area are patterned, undesired issues occur such as generation of bird's beaks due to side wall oxidation so that the performance of transistors is degraded. To avoid this, during a process of forming laminated gate electrodes of flash memories, the second polysilicon layer is not patterned but left.
A flash memory can function as a MOS transistor by connecting a wiring to the floating gate of a flash memory. A transistor can be formed by using flash memory manufacture processes. This transistor is called first polysilicon transistor.
In order to form an electrically insulated floating gate of a flash memory, first, first polysilicon layers covering the active regions are formed in a parallel stripe shape and covered with an ONO film. After the ONO film is patterned, a second polysilicon layer is deposited on the whole substrate surface. By disposing a control gate mask pattern crossing parallel stripes of the first polysilicon layers, the second polysilicon layers, ONO films and first polysilicon layers are etched to form laminated electrodes.
Most of manufacture processes are used in common in the flash memory area and first polysilicon transistor area, separately from the peripheral circuit area using single-layer gate electrodes. Although the second polysilicon layer is formed secondarily in a first polysilicon transistor area, this layer is not necessary in terms of electric sense. The first and second polysilicon layers may be patterned in the same shape. The first polysilicon layer is left in the first polysilicon transistor area and removed in its peripheral area. The peripheral edge of the first polysilicon layer extends outside the first polysilicon transistor area. The ONO film is formed on the upper surface and peripheral side wall of the first polysilicon layer.
The second polysilicon layer is formed thereafter. By masking out the peripheral circuit area, the second polysilicon layer, ONO film and first polysilicon layer in the flash memory area and first polysilicon transistor area are etched to form laminated gate electrodes. It is difficult to completely remove the ONO film on the peripheral side wall of the first polysilicon layer.
After the side walls of the laminated gate electrodes are thermally oxidized, a silicon nitride film is deposited on the whole substrate surface, and side wall spacers are formed on the side walls of the laminated gate electrodes by reactive ion etching (RIE). Side walls are also formed on the peripheral side walls of the second polysilicon layer covering the peripheral circuit area. Thereafter, the second polysilicon layer in the peripheral circuit area is etched. It is not easy to completely remove the peripheral side wall of the second polysilicon layer.
The second polysilicon layer is patterned by different processes for the laminated gate electrode area (flash memory area+first polysilicon transistor area) and for the peripheral circuit area. As described above, residues are likely to be formed in the border area between the laminated gate electrode area and single-layer gate electrode layer. Residues are easy to be peeled off, forming dusts.
Description will be made by referring to the accompanying drawings. FIGS. 10A and 10B are a partial plan view of a flash memory area adjacent to a peripheral circuit area and a partial plan view of a first polysilicon transistor area adjacent to the peripheral circuit area. FIGS. 11A1 to 11A4 and FIGS. 11B1 to 11B4 are cross sectional views showing the structures of the flash memory area and first polysilicon transistor area during manufacture processes.
As shown in FIGS. 10A and 10B, in the flash memory area and first polysilicon transistor area, a plurality of active regions AR long in vertical direction are defined in parallel and surrounded by an isolation region ISO. In the flash memory area, a plurality of first polysilicon layers p1s are patterned in stripe shape, being mutually separated and covering each active region AR. In the first polysilicon transistor area, the first polysilicon layer p1s is patterned in a single plain shape covering the whole area as shown by a broken line p1p. A laminated insulating layer ONO of an oxide film/a nitride film/an oxide film is formed covering the first polysilicon layer p1 (p1s and p1p are collectively represented by p1). The laminated insulating layer ONO has a large height on the side wall of the first polysilicon layer p1.
A second polysilicon layer p2p is formed above the whole substrate surface, covering the first polysilicon layer p1 and upper laminated insulating layer ONO. In the area inner than a border line DSG, the second polysilicon layer p2p, and the underlying laminated insulating layer ONO and first polysilicon layer p1 are etched in a shape of the control gate electrode CG and gate electrode G by using the same mask. In the area outer than the border line DSG, the whole polysilicon layer is left. Since the laminated insulating layer ONO has a large height at the peripheral side wall of the first polysilicon layer, etching residues are formed.
FIG. 11A1 is a cross sectional view along a direction of the active region AR in the flash memory area shown in FIG. 10A. FIG. 11B1 is a cross sectional view along a direction of the laminated gate electrode G in the first polysilicon transistor area shown in FIG. 10B. Although the flat second polysilicon layer p2, laminated insulating layer ONO and first polysilicon layer p1 are etched, the laminated insulating layer ONO on the peripheral side wall of the first polysilicon layer p1 is left, forming an ONO fence OF. The ONO fence OF between the control gate electrodes CG is hard to be peeled off because the distance between the control gate electrodes CG is short as shown in FIG. 10A. In the lower area of FIG. 10A, an elongated U-character shaped ONO fence OF is formed and is easy to be peeled off. The ONO fence at the peripheral side wall of the first polysilicon transistor area has no support as shown in FIG. 10B and is extremely long so that it is very easy to be peeled off.
FIGS. 11A2 and 11B2 are cross sectional views along the direction of the laminated gate electrodes CG and G in the flash memory area and first polysilicon transistor area. The side wall of the laminated gate electrode (including a region of only the second polysilicon layer p2 in the flash memory area) is oxidized, and after ion implantation, the side wall of the laminated gate electrode is oxidized again. The oxide film ox is shown in FIGS. 11A2 and 11B2, but will be omitted for simplicity in other figures. Thereafter, a silicon nitride layer is deposited and anisotropic etching is performed to form a side wall SW1 of silicon nitride on the side wall of the laminated gate electrode. A side wall SW1 is also formed on the side wall of the second polysilicon layer in the peripheral circuit area. Side walls SW3 are formed on the side walls of the ONO fence OF. Even in this state, it cannot be said that the strength of the ONO fence is sufficient. After the laminated gate electrode structure is formed in the laminated gate area, single-layer gate electrodes are formed in the peripheral circuit area.
With reference to FIGS. 10A and 10B, the area inner than a border line DP2 is covered with a resist mask, and the second polysilicon layer p2 in the peripheral circuit area outer than the border line DP2 is patterned to form gate electrodes of the peripheral circuit. An unnecessary second polysilicon layer p2 is etched and removed.
As shown in FIGS. 11A3 and 11B3, the side wall SW1 of silicon nitride formed on the peripheral side wall of the second polysilicon layer p2 in the peripheral circuit area loses the support of the second polysilicon layer, forming a silicon nitride pillar SNP in a wall shape (a pillar shape in cross section).
By using a resist mask, contact holes are formed thorough the second polysilicon layer and laminated insulating layer ONO of the first polysilicon transistor to expose the first polysilicon layer. In the peripheral circuit area, impurity ion implantation is performed on both side of the gate electrode, a silicon oxide layer is deposited, and RIE is performed to form side walls of silicon oxide.
As shown in FIGS. 11A4 and 11B4, also in the border area between the flash memory area and first polysilicon transistor area, oxide film side walls SW2 are formed on the already formed nitride film side wall SW1 and side walls of the SiN pillar SNP. Side walls SW2 are formed also on the side walls of the ONO fence OF. Even if the side walls SW2 are formed, the ONO fence OF and SiN pillar SNP are easy to be peeled off, forming dusts and lowering a yield.
Japanese Patent Laid-open Publication No. HEI-10-163456 proposes that while a first polysilicon film is patterned, a peripheral circuit area is covered with the first polysilicon layer, and after an ONO film is formed, the ONO film and first polysilicon film are etched to leave the first polysilicon film in the peripheral area of the peripheral circuit area. The ONO film on the side wall of the first polysilicon film is left together with the first polysilicon film to prevent generation of ONO fence of thin fence shape.
Japanese Patent Laid-open Publication No. 2000-286350 proposes that the end portion of a first polysilicon film is covered with a dummy pattern second polysilicon film to prevent an ONO film on the side wall of the first polysilicon film from being exposed by etching and dusts from being generated.
By covering the end portion of the striped first polysilicon film above the active region in the memory area, with the dummy pattern second polysilicon film, generation of a long ONO fence without support can be prevented, to prevent peeling-off.